1. Field of the Invention
The present general inventive concept relates to a multilayer printed circuit board (PCB), and more particularly, to a multilayer PCB having a stitching capacitor.
2. Description of the Related Art
A multi-layer PCB comprises a plurality of chips and electronic components, a plurality of signal layers communicating with each other through a signal current, and a ground layer and a power layer through which a return current corresponding to the signal current flows. One or more openings (not shown) are disposed in each layer of the multilayer PCB. A via is disposed at the one or more openings to electrically connect to each layer.
FIG. 1 is a perspective view illustrating a conventional multilayer PCB, and FIG. 2 is a plane view illustrating the conventional multiplayer PCB of FIG. 1.
Referring to FIG. 1, the conventional multilayer PCB comprises a first signal layer 10, which is the uppermost layer of the PCB, and a second signal layer 40, which is the lowermost layer of the PCB. A ground layer 20 and a power layer 30 are disposed between the first signal layer 10 and the second signal layer 40. A signal via 50 is formed between the first signal layer 10 and the second signal layer 40 to pass a signal current 1 therebetween.
In this case, a signal transmitted to a target chip (not shown) disposed at the second signal layer 40 from a source chip (not shown) disposed at the first signal layer 10 is represented by the signal current 1 illustrated by a solid line in FIG. 1.
In addition, a return current 2 is generated according to the signal current 1. The signal current 1 and the return current 2 form a current loop together. As illustrated in FIG. 1, the return current 2 flows through a path that can have a minimal impedance, since the return current 2 flows through the shortest possible path (i.e., between the power layer 30 and the ground layer 20 adjacent to the signal current 1). The return current 2 may flow through a grounded guard covering the signal current 1 at the first signal layer 10 and the second signal layer 40, which is a path extending directly through the ground layer 20 and the power layer 30 that are used as a reference surface.
Alternatively, a return current 3 can flow through a decoupling capacitor 60 from the power layer 30 to the ground layer 20. However, in this case the impedance that corresponds to the return current 3 is greater than when the return current 2 is allowed to flow directly through the reference surface (i.e., the shortest path).
Thus, the conventional multilayer PCB provides a path of the return current 3 through the reference surface using a plurality of decoupling capacitors 60 disposed all over the PCB. The decoupling capacitor 60 is formed at the first signal layer 10 and includes a power via 61 connected to the power layer 30 and a ground via 62 connected to the ground layer 20.
Referring to FIGS. 1 and 2, the decoupling capacitors 60 allow the return current 3 to form a current loop by returning from the power layer 30, which is used as the reference surface of the second signal layer 40, to the ground layer 20, which is used as the reference surface of the first signal layer 10, by passing through the power via 61 and the ground via 62 of the decoupling capacitors 60.
However, as illustrated in FIG. 2, a loop area (A) formed by the signal current 1 and the return current 3 increases. The increase in the loop area (A) causes an increase in electromagnetic interference (EMI), having a negative effect on nearby electronic components. The increase in EMI may prevent the PCB from functioning properly when the signal current 1, which is transferred between the first and second signal layers 10 and 40, is controlled by a frequency value.